The present application relates to semiconductor device fabrication, and more particularly to the fabrication of a grated metal-insulator-metal (MIM) capacitor structure that has enhanced capacitance.
On-chip capacitors including metal-insulator-metal (MIM) capacitors are essential for many semiconductor chips. For example, MIM capacitors are frequently utilized as decoupling capacitors for mitigating power supply or switching noise caused by changes in current flowing in an integrated chip. MIM capacitors are often integrated into a back-end-of-the-line (BEOL) metallization stack, at a positon between an underlying first metallization layer and an overlying second metallization layer. When integrated, a MIM capacitor is commonly formed as a stacked structure including planar electrode plates. Thus, to ensure a minimal capacitance, a large chip area is usually required for a MIM capacitor which, in turn, adversely increases the chip size and thus the cost of the chip. There is thus a need for providing on-chip MIM capacitors that have enhanced capacitance without increasing the size of the chip or the cost of the chip.